有哪位高手告诉我，我用一开机就总是出现To interrupt normal post,press enter 字样_百度知道
有哪位高手告诉我，我用一开机就总是出现To interrupt normal post,press enter 字样
我现在始终开不起机，到底怎样在BIOS中进行设置哟
我有更好的答案
重装下系统。如果没更改过BIOS，那就不要去乱弄了，因为一般都是设置好的，而且按提示信息，跟BIOS没什么关系，是系统问题
采纳率：35%
因为同类软件，互不兼容，“木马查杀”里的：“360系统急救箱”。试试开机，出完电脑品牌后，按F8，回车，立即清理！360安全卫士，系统修复！这是解决方法：（原创，引用请说明作者：力王历史）1。再使用，按下去试试，多余类似软件，如：多款播放器，多款杀毒软件等，卸载多余的，只留一款！3，一键修复！4。再不行，拔下显卡和内存条。硬件有问题，新年快乐，万事如意，更换内存插槽等。再不行，进安全模式，彻底删除文件！360安全卫士，扫描插件。再不行，橡皮擦擦，再用毛刷：显卡驱动！7。再开机，如果还是不行，需要“一键还原”或“重装系统”了！ 8！【关键一步】2！【台式机】5。检查是否有同类功能的，系统修复，全选，回车，回车，回车，进安全模式里：360安全卫士，回车，到桌面后！“隔离区”的东西，彻底删除，下载“驱动人生”，升级：开始急救！重启后，点开“文件恢复区”，全选，立即修复！【关键一步】网络修复！【关键一步】6，开始修复！再点，高级启动选项，最后一次正确配置，清理插槽灰尘和风扇，杀毒软件，全盘杀毒你好
这是自检POST报错，拔掉主板电池清除CMOS信息 过十分钟左右再把电池装回去,提示信息丢失 选YES LOAD DEFAULT 看是否报错
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Interrupt exception handling flow（中断异常处理流程）
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Interrupt exception handling flow（中断异常处理流
关注微信公众号From Wikipedia, the free encyclopedia
This article needs additional citations for . Please help
by . Unsourced material may be challenged and removed. (February 2014) ()
interrupt sources and processor handling
In , an interrupt is a signal to the
emitted by hardware or software indicating an event that needs immediate attention. An interrupt alerts the processor to a high-priority condition requiring the interruption of the current code the processor is executing. The processor responds by suspending its current activities, saving its , and executing a
(or an interrupt service routine, ISR) to deal with the event. This interruption is temporary, and, after the interrupt handler finishes, the processor resumes normal activities. There are two types of interrupts: hardware interrupts and software interrupts.
Hardware interrupts are used by devices to communicate that they require attention from the . Internally, hardware interrupts are implemented using electronic alerting signals that are sent to the processor from an external device, which is either a part of the computer itself, such as a , or an external . For example, pressing a key on the
or moving the
triggers hardware interrupts that cause the processor to read the keystroke or mouse position. Unlike the software type (described below), hardware interrupts are
and can occur in the middle of instruction execution, requiring additional care in programming. The act of initiating a hardware interrupt is referred to as an
A software interrupt is caused either by an exceptional condition in the processor itself, or a special
which causes an interrupt when it is executed. The former is often called a
and is used for errors or events occurring during program execution that are exceptional enough that they cannot be handled within the program itself. For example, a divide-by-zero exception will be thrown if the processor's
is commanded to divide a number by zero as this instruction is an error and impossible. The operating system will catch this exception, and can choose to abort the instruction. Software interrupt instructions can function similarly to
and are used for a variety of purposes, such as to request services from , like interrupts sent to and from a
to request reading or writing of data to and from the disk.
Each interrupt has its own interrupt handler. The number of hardware interrupts is limited by the number of interrupt request (IRQ) lines to the processor, but there may be hundreds of different software interrupts. Interrupts are a commonly used technique for , especially in . Such a system is said to be interrupt-driven.
Interrupts are similar to , the difference being that signals are used for , mediated by the kernel (possibly via system calls) and handled by processes, while interrupts are mediated by the processor and handled by the . The kernel may pass an interrupt as a signal to the process that caused it (typical examples are , ,
Hardware interrupts were introduced as an optimization, eliminating unproductive waiting time in , waiting for external events. They may be implemented in hardware as a distinct system with control lines, or they may be integrated into the memory subsystem.
If implemented in hardware, an interrupt controller circuit such as the IBM PC's
(PIC) may be connected between the interrupting device and the processor's interrupt pin to
several sources of interrupt onto the one or two CPU lines typically available. If implemented as part of the , interrupts are mapped into the system's memory .
Interrupts can be categorized into these different types:
Maskable interrupt (): a hardware interrupt that may be ignored by setting a bit in an 's (IMR) bit-mask.
(NMI): a hardware interrupt that lacks an associated bit-mask, so that it can never be ignored. NMIs are used for the highest priority tasks such as timers, especially .
(IPI): a special case of interrupt that is generated by one processor to interrupt another processor in a
Software interrupt: an interrupt generated within a processor by executing an instruction. Software interrupts are often used to implement
because they result in a subroutine call with a
Spurious interrupt: a hardware interrupt that is unwanted. They are typically generated by system conditions such as
on an interrupt line or through incorrectly designed hardware.
Processors typically have an internal interrupt mask which allows software to ignore all external hardware interrupts while it is set. Setting or clearing this mask may be faster than accessing an interrupt mask register (IMR) in a PIC or disabling interrupts in the device itself. In some cases, such as the
architecture, disabling and enabling interrupts on the proces however, it may actually be slower.
An interrupt that leaves the machine in a well-defined state is called a precise interrupt. Such an interrupt has four properties:
is saved in a known place.
All instructions before the one pointed to by the PC have fully executed.
No instruction beyond the one pointed to by the PC has been executed (that is no prohibition on instruction beyond that in PC, it is just that any changes they make to registers or memory must be undone before the interrupt happens).
The execution state of the instruction pointed to by the PC is known.
An interrupt that does not meet these requirements is called an imprecise interrupt.
The phenomenon where the overall system performance is severely hindered by excessive amounts of processing time spent handling interrupts is called an .
Types of interrupts[]
A level-triggered interrupt is an interrupt signaled by maintaining the interrupt line at a high or low . A device wishing to signal a Level-triggered interrupt drives the
line to its active level (high or low), and then holds it at that level until it is serviced. It ceases asserting the line when the CPU commands it to or otherwise handles the condition that caused it to signal the interrupt.
Typically, the processor samples the interrupt input at predefined times during each bus cycle such as state T2 for the
microprocessor. If the interrupt isn't active when the processor samples it, the CPU doesn't see it. One possible use for this type of interrupt is to minimize spurious signals from a noisy interrupt line: a spurious pulse will often be so short that it is not noticed.
Multiple devices may share a level-triggered interrupt line if they are designed to. The interrupt line must have a pull-down or
so that when not actively driven it settles to its inactive state. Devices actively assert the line to indicate an outstanding interrupt, but let the line float (do not actively drive it) when not signalling an interrupt. The line is then in its asserted state when any (one or more than one) of the sharing devices is signalling an outstanding interrupt.
Level-triggered interrupt is favored by some because it is easy to share the
line without losing the interrupts, when multiple shared devices interrupt at the same time. Upon detecting assertion of the interrupt line, the CPU must search through the devices sharing the
line until one who triggered the interrupt is detected. After servicing this device, the CPU may recheck the interrupt line status to determine whether any other devices also needs service. If the line is now de-asserted, the CPU avoids checking the remaining devices on the line. Since some devices interrupt more frequently than others, and other device interrupts are particularly expensive, a careful ordering of device checks is employed to increase efficiency. The original
standard mandated level-triggered interrupts because of this advantage of sharing interrupts.
There are also serious problems with sharing level-triggered interrupts. As long as any device on the line has an outstanding request for service the line remains asserted, so it is not possible to detect a change in the status of any other device. Deferring servicing a low-priority device is not an option, because this would prevent detection of service requests from higher-priority devices. If there is a device on the line that the CPU does not know how to service, then any interrupt from that device permanently blocks all interrupts from the other devices.
An edge-triggered interrupt is an interrupt signalled by a
on the interrupt line, either a falling edge (high to low) or a rising edge (low to high). A device, wishing to signal an interrupt, drives a pulse onto the line and then releases the line to its inactive state. If the pulse is too short to be detected by
then special hardware may be required to detect the edge.
Multiple devices may share an edge-triggered interrupt line if they are designed to. The interrupt line must have a pull-down or pull-up resistor so that when not actively driven it settles to one particular state. Devices signal an interrupt by briefly driving the line to its non-default state, and let the line float (do not actively drive it) when not signalling an interrupt. This type of connection is also referred to as . The line then carries all the pulses generated by all the devices. (This is analogous to the
on some buses and trolleys that any passenger can pull to signal the driver that they are requesting a stop.) However, interrupt pulses from different devices may merge if they occur close in time. To avoid losing interrupts the CPU must trigger on the trailing edge of the pulse (e.g. the rising edge if the line is pulled up and driven low). After detecting an interrupt the CPU must check all the devices for service requirements.
Edge-triggered interrupts do not suffer the problems that level-triggered interrupts have with sharing. Service of a low-priority device can be postponed arbitrarily, and interrupts will continue to be received from the high-priority devices that are being serviced. If there is a device that the CPU does not know how to service, it may cause a spurious interrupt, or even periodic spurious interrupts, but it does not interfere with the interrupt signalling of the other devices. However, it is fairly easy for an edge triggered interrupt to be missed - for example if interrupts have to be masked for a period - and unless there is some type of hardware latch that records the event it is impossible to recover. Such problems caused many "lockups" in early computer hardware because the processor did not know it was expected to do something. More modern hardware often has one or more interrupt status registers that latch th well written edge-driven interrupt software often checks such registers to ensure events are not missed.
The elderly
(ISA) bus uses edge-triggered interrupts, but does not mandate that devices be able to share them. The
also uses edge-triggered interrupts. Many older devices assume that they have exclusive use of their interrupt line, making it electrically unsafe to share them. However, ISA motherboards include pull-up resistors on the IRQ lines, so well-behaved devices share ISA interrupts just fine.
Some systems use a hybrid of level-triggered and edge-triggered signalling. The hardware not only looks for an edge, but it also verifies that the interrupt signal stays active for a certain period of time.
A common use of a hybrid interrupt is for the NMI (non-maskable interrupt) input. Because NMIs generally signal major – or even catastrophic – system events, a good implementation of this signal tries to ensure that the interrupt is valid by verifying that it remains active for a period of time. This 2-step approach helps to eliminate false interrupts from affecting the system.
A message-signalled interrupt does not use a physical interrupt line. Instead, a device signals its request for service by sending a short message over some communications medium, typically a . The message might be of a type reserved for interrupts, or it might be of some pre-existing type such as a memory write.
Message-signalled interrupts behave very much like edge-triggered interrupts, in that the interrupt is a momentary signal rather than a continuous condition. Interrupt-handling software treats the two in much the same manner. Typically, multiple pending message-signalled interrupts with the same message (the same virtual interrupt line) are allowed to merge, just as closely spaced edge-triggered interrupts can merge.
Message-signalled
can be shared, to the extent that the underlying communication medium can be shared. No additional effort is required.
Because the identity of the interrupt is indicated by a pattern of data bits, not requiring a separate physical conductor, many more distinct interrupts can be efficiently handled. This reduces the need for sharing. Interrupt messages can also be passed over a serial bus, not requiring any additional lines.
, a serial computer bus, uses
exclusively.
analogy applied to , the term doorbell or doorbell interrupt is often used to describe a mechanism whereby a
system can signal or notify a
device that there is some work to be done. Typically, the software system will place data in some well-known and mutually agreed upon memory location(s), and "ring the doorbell" by writing to a different memory location. This different memory location is often called the doorbell region, and there may even be multiple doorbells serving different purposes in this region. It is this act of writing to the doorbell region of memory that "rings the bell" and notifies the hardware device that the data are ready and waiting. The hardware device would now know that the data are valid and can be acted upon. It would typically write the data to a , or send them over a , or
them, etc.
The term doorbell interrupt is usually a . It's similar to an interrupt, because it causes some work to b however, the doorbell region is sometimes implemented as a
region, sometimes the doorbell region writes through to physical device , and sometimes the doorbell region is hardwired directly to physical device registers. When either writing through or directly to physical device registers, this may cause a real interrupt to occur at the device's central processor unit (), if it has one.
Doorbell interrupts can be compared to , as they have some similarities.
Multiple devices sharing an interrupt line (of any triggering style) all act as spurious interrupt sources with respect to each other. With many devices on one line the workload in servicing interrupts grows in proportion to the square of the number of devices. It is therefore preferred to spread devices evenly across the available interrupt lines. Shortage of interrupt lines is a problem in older system designs where the interrupt lines are distinct physical conductors. Message-signalled interrupts, where the interrupt line is virtual, are favored in new system architectures (such as ) and relieve this problem to a considerable extent.
Some devices with a poorly designed programming interface provide no way to determine whether they have requested service. They may lock up or otherwise misbehave if serviced when they do not want it. Such devices cannot tolerate spurious interrupts, and so also cannot tolerate sharing an interrupt line.
cards, due to often cheap design and construction, are notorious for this problem. Such devices are becoming much rarer, as
becomes cheaper and new system architectures mandate shareable interrupts.
Performance issues[]
Interrupts provide low overhead and good
at low load, but degrade significantly at high interrupt rate unless care is taken to prevent several pathologies. These are various forms of , when the system spends all of its time processing interrupts to the exclusion of other required tasks. Under extreme conditions, a large number of interrupts (like very high network traffic) may completely stall the system. To avoid such problems, an
must schedule network interrupt handling as carefully as it schedules process execution.
With multi-core processors, additional performance improvements in interrupt handling can be achieved through
(RSS) when
are used. Such NICs provide multiple receive
associated to by routing each of those interrupts to different cores, processing of the interrupt requests triggered by the network traffic received by a single NIC can be distributed among multiple cores. Distribution of the interrupts among cores can be performed automatically by the operating system, or the routing of interrupts (usually referred to as IRQ affinity) can be manually configured.
A purely software-based implementation of the receiving traffic distribution, known as receive packet steering (RPS), distributes received traffic among cores later in the data path, as part of the
functionality. Advantages of RPS over RSS include no requirements for specific hardware, more advanced traffic distribution filters, and reduced rate of interrupts produced by a NIC. As a downside, RPS increases the rate of
(IPIs). Receive flow steering (RFS) takes the software-based approach furthe further performance improvements are achieved by processing interrupt requests by the same cores on which particular network packets will be consumed by the targeted application.
Typical uses of interrupts include the following: system timers, disk I/O, power-off signals, and . Other interrupts exist to transfer d sense key- or anything else the equipment must do.
Another typical use is to generate periodic interrupts by dividing the output of a crystal oscillator and having an interrupt handler count the interrupts in order for a processor to keep time. These periodic interrupts are often used by the OS's task
to reschedule the priorities of running . Some older computers generated periodic interrupts from the
because it was controlled by the utilities to eliminate long-term drift of electric clocks.
For example, a disk interrupt signals the completion of a data transfer from or to a process waiting to read or write a file starts up again. As another example, a power-off interrupt predicts or requests a loss of power, allowing the computer equipment to perform an orderly shut-down. Also, interrupts are used in
features for buffering events like .
Interrupts are used to allow emulation of instructions which are unimplemented on certain models in a computer line. For example
instructions may be implemented in hardware on some systems and emulated on lower-cost systems. Execution of an unimplemented instruction will cause an interrupt. The operating system interrupt handler will recognize the occurrence on an unimplemented instruction, interpret the instruction in a software routine, and then return to the interrupting program as if the instruction had been executed. This provides application software portability across the entire line.
Jonathan C Alessandro R Greg Kroah-Hartman (2005).
(PDF). . p. 269 2014. Then it's just a matter of cleaning up, running software interrupts, and getting back to regular work. The "regular work" may well have changed as a result of an interrupt (the handler could wake_up a process, for example), so the last thing that happens on return from an interrupt is a possible rescheduling of the processor.
Tom H Willem de Bruijn (May 9, 2014). . Linux kernel documentation.
(PDF). . June 2014. p. 1 2014.
Jonathan Corbet (November 17, 2009). .
Jake Edge (April 7, 2010). .
Thusoo, Shalesh, et. al. . Google Patents 2017.
Altera Corporation (2009).
(PDF). p. 4 2017.
Look up  or
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