quartus ii 3.0破解方法
quartus ii 3.0破解方法
09-11-16 &匿名提问
貌似改成两个[3..0]的脚吧？用VHDL语言编写程序，让他自己去生成一个三八译码器就好了嘛，程序如下：library IEEE; use IEEE.Std_Logic_1164.ALL; entity decoder IS port (in1 : in Std_Logic_Vector(2 downto 0); out1,out2 : out Std_Logic_Vector(3 downto 0));
architecture decoder38 of decoder is begin decoder:process(in1) begin case in1 is when&000&=&out1&=&&; when&001&=&out1&=&&; when&010&=&out1&=&&; when&011&=&out1&=&&; when&100&=&out2&=&&; when&101&=&out2&=&&; when&110&=&out2&=&&; when&111&=&out2&=&&; when others=&
end decoder38; 自己去实现吧，哈哈……,貌似改成两个[3..0]的脚吧？用VHDL语言编写程序，让他自己去生成一个三八译码器就好了嘛，程序如下：,library IEEE; ,use IEEE.Std_Logic_1164.ALL; ,entity decoder IS ,port (in1 : in Std_Logic_Vector(2 downto 0); ,out1,out2 : out Std_Logic_Vector(3 downto 0)); , ,architecture decoder38 of decoder is ,begin ,decoder:process(in1) ,begin ,case in1 is ,when&000&=&out1&=&&; ,when&001&=&out1&=&&; ,when&010&=&out1&=&&; ,when&011&=&out1&=&&; ,when&100&=&out2&=&&; ,when&101&=&out2&=&&; ,when&110&=&out2&=&&; ,when&111&=&out2&=&&; ,when others=& , , ,end decoder38; ,自己去实现吧，哈哈……,,貌似改成两个[3..0]的脚吧？用VHDL语言编写程序，让他自己去生成一个三八译码器就好了嘛，程序如下：,library IEEE; ,use IEEE.Std_Logic_1164.ALL; ,entity decoder IS ,port (in1 : in Std_Logic_Vector(2 downto 0); ,out1,out2 : out Std_Logic_Vector(3 downto 0)); , ,architecture decoder38 of decoder is ,begin ,decoder:process(in1) ,begin ,case in1 is ,when&000&=&out1&=&&; ,when&001&=&out1&=&&; ,when&010&=&out1&=&&; ,when&011&=&out1&=&&; ,when&100&=&out2&=&&; ,when&101&=&out2&=&&; ,when&110&=&out2&=&&; ,when&111&=&out2&=&&; ,when others=& , , ,end decoder38; ,自己去实现吧，哈哈……,,貌似改成两个[3..0]的脚吧？用VHDL语言编写程序，让他自己去生成一个三八译码器就好了嘛，程序如下：,library IEEE; ,use IEEE.Std_Logic_1164.ALL; ,entity decoder IS ,port (in1 : in Std_Logic_Vector(2 downto 0); ,out1,out2 : out Std_Logic_Vector(3 downto 0)); , ,architecture decoder38 of decoder is ,begin ,decoder:process(in1) ,begin ,case in1 is ,when&000&=&out1&=&&; ,when&001&=&out1&=&&; ,when&010&=&out1&=&&; ,when&011&=&out1&=&&; ,when&100&=&out2&=&&; ,when&101&=&out2&=&&; ,when&110&=&out2&=&&; ,when&111&=&out2&=&&; ,when others=& , , ,end decoder38; ,自己去实现吧，哈哈……,,貌似改成两个[3..0]的脚吧？用VHDL语言编写程序，让他自己去生成一个三八译码器就好了嘛，程序如下：,library IEEE; ,use IEEE.Std_Logic_1164.ALL; ,entity decoder IS ,port (in1 : in Std_Logic_Vector(2 downto 0); ,out1,out2 : out Std_Logic_Vector(3 downto 0)); , ,architecture decoder38 of decoder is ,begin ,decoder:process(in1) ,begin ,case in1 is ,when&000&=&out1&=&&; ,when&001&=&out1&=&&; ,when&010&=&out1&=&&; ,when&011&=&out1&=&&; ,when&100&=&out2&=&&; ,when&101&=&out2&=&&; ,when&110&=&out2&=&&; ,when&111&=&out2&=&&; ,when others=& , , ,end decoder38; ,自己去实现吧，哈哈……,,貌似改成两个[3..0]的脚吧？用VHDL语言编写程序，让他自己去生成一个三八译码器就好了嘛，程序如下：,library IEEE; ,use IEEE.Std_Logic_1164.ALL; ,entity decoder IS ,port (in1 : in Std_Logic_Vector(2 downto 0); ,out1,out2 : out Std_Logic_Vector(3 downto 0)); , ,architecture decoder38 of decoder is ,begin ,decoder:process(in1) ,begin ,case in1 is ,when&000&=&out1&=&&; ,when&001&=&out1&=&&; ,when&010&=&out1&=&&; ,when&011&=&out1&=&&; ,when&100&=&out2&=&&; ,when&101&=&out2&=&&; ,when&110&=&out2&=&&; ,when&111&=&out2&=&&; ,when others=& , , ,end decoder38; ,自己去实现吧，哈哈……,,貌似改成两个[3..0]的脚吧？用VHDL语言编写程序，让他自己去生成一个三八译码器就好了嘛，程序如下：,library IEEE; ,use IEEE.Std_Logic_1164.ALL; ,entity decoder IS ,port (in1 : in Std_Logic_Vector(2 downto 0); ,out1,out2 : out Std_Logic_Vector(3 downto 0)); , ,architecture decoder38 of decoder is ,begin ,decoder:process(in1) ,begin ,case in1 is ,when&000&=&out1&=&&; ,when&001&=&out1&=&&; ,when&010&=&out1&=&&; ,when&011&=&out1&=&&; ,when&100&=&out2&=&&; ,when&101&=&out2&=&&; ,when&110&=&out2&=&&; ,when&111&=&out2&=&&; ,when others=& , , ,end decoder38; ,自己去实现吧，哈哈……,,貌似改成两个[3..0]的脚吧？用VHDL语言编写程序，让他自己去生成一个三八译码器就好了嘛，程序如下：,library IEEE; ,use IEEE.Std_Logic_1164.ALL; ,entity decoder IS ,port (in1 : in Std_Logic_Vector(2 downto 0); ,out1,out2 : out Std_Logic_Vector(3 downto 0)); , ,architecture decoder38 of decoder is ,begin ,decoder:process(in1) ,begin ,case in1 is ,when&000&=&out1&=&&; ,when&001&=&out1&=&&; ,when&010&=&out1&=&&; ,when&011&=&out1&=&&; ,when&100&=&out2&=&&; ,when&101&=&out2&=&&; ,when&110&=&out2&=&&; ,when&111&=&out2&=&&; ,when others=& , , ,end decoder38; ,自己去实现吧，哈哈……,,貌似改成两个[3..0]的脚吧？用VHDL语言编写程序，让他自己去生成一个三八译码器就好了嘛，程序如下：,library IEEE; ,use IEEE.Std_Logic_1164.ALL; ,entity decoder IS ,port (in1 : in Std_Logic_Vector(2 downto 0); ,out1,out2 : out Std_Logic_Vector(3 downto 0)); , ,architecture decoder38 of decoder is ,begin ,decoder:process(in1) ,begin ,case in1 is ,when&000&=&out1&=&&; ,when&001&=&out1&=&&; ,when&010&=&out1&=&&; ,when&011&=&out1&=&&; ,when&100&=&out2&=&&; ,when&101&=&out2&=&&; ,when&110&=&out2&=&&; ,when&111&=&out2&=&&; ,when others=& , , ,end decoder38; ,自己去实现吧，哈哈……,,貌似改成两个[3..0]的脚吧？用VHDL语言编写程序，让他自己去生成一个三八译码器就好了嘛，程序如下：,library IEEE; ,use IEEE.Std_Logic_1164.ALL; ,entity decoder IS ,port (in1 : in Std_Logic_Vector(2 downto 0); ,out1,out2 : out Std_Logic_Vector(3 downto 0)); , ,architecture decoder38 of decoder is ,begin ,decoder:process(in1) ,begin ,case in1 is ,when&000&=&out1&=&&; ,when&001&=&out1&=&&; ,when&010&=&out1&=&&; ,when&011&=&out1&=&&; ,when&100&=&out2&=&&; ,when&101&=&out2&=&&; ,when&110&=&out2&=&&; ,when&111&=&out2&=&&; ,when others=& , , ,end decoder38; ,自己去实现吧，哈哈……,,貌似改成两个[3..0]的脚吧？用VHDL语言编写程序，让他自己去生成一个三八译码器就好了嘛，程序如下：,library IEEE; ,use IEEE.Std_Logic_1164.ALL; ,entity decoder IS ,port (in1 : in Std_Logic_Vector(2 downto 0); ,out1,out2 : out Std_Logic_Vector(3 downto 0)); , ,architecture decoder38 of decoder is ,begin ,decoder:process(in1) ,begin ,case in1 is ,when&000&=&out1&=&&; ,when&001&=&out1&=&&; ,when&010&=&out1&=&&; ,when&011&=&out1&=&&; ,when&100&=&out2&=&&; ,when&101&=&out2&=&&; ,when&110&=&out2&=&&; ,when&111&=&out2&=&&; ,when others=& , , ,end decoder38; ,自己去实现吧，哈哈……,,貌似改成两个[3..0]的脚吧？用VHDL语言编写程序，让他自己去生成一个三八译码器就好了嘛，程序如下：,library IEEE; ,use IEEE.Std_Logic_1164.ALL; ,entity decoder IS ,port (in1 : in Std_Logic_Vector(2 downto 0); ,out1,out2 : out Std_Logic_Vect
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Quartus II9.1 破解问题解决方法
Quartus II 9.1 安装俊龙科技提供的SP1、SP2版本，安装时先安装SP1，在安装SP2，安装完成后进行破解。按照网上提供的破解器和破解方法进行破解，在实际过程编译的时候出现下面问题：
提示信息表明：破解失败，license不匹配。
解决办法：重新下载破解器，按照破解说明破解成功。破解成功后界面如下所示：
破解文件链接如下：
我下载的就是9.1的SP2 。还没安装呢
这个很及时喔
先安装SP1 再安装SP2 呵呵！
LZ&& 能把你用的破解器发下吗？我用了你的破解文件还是不能解决问题
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