JAGUAR台达变频器故障代码码err10是什么意思

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The AMD Jaguar Family 16h is a low-power microarchitecture designed by , and used in
succeeding the
microarchitecture in 2013 and being succeeded by AMD's
in 2014. It is two-way
and capable of . It is used in AMD's Semi-Custom Business Unit as a design for custom processors and is used by AMD in four product families: Kabini aimed at notebooks and mini PCs, Temash aimed at tablets, Kyoto aimed at micro-servers, and the G-Series aimed at embedded applications. Both the
use chips based on the Jaguar microarchitecture, with more powerful GPUs than AMD sells in its own commercially available Jaguar APUs.
32 KiB instruction + 32 KiB data L1
per core, L1 cache includes parity error detection
16-way, 1–2 MiB unified L2 cache shared by two or four cores, L2 cache is protected from errors by the use of error correcting code
Integrated
Two-way integer execution
Two-way 128-bit wide floating-point and packed integer execution
Integer hardware divider
Consumer processors support two DDR3L DIMMs in one channel at frequencies up to ;MHz
Server processors support two DDR3 DIMMS in one channel at frequencies up to ;MHz with ECC
As a SoC (not just an APU) it integrates
Jaguar does not feature
(CMT), meaning that execution resources are not shared between cores
The Jaguar core has support for the following instruction sets and instructions: , , , , , , , , , , CLMUL, , BMI1, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT,
(POPCNT/LZCNT), and .
Over 10% increase in clock frequency
Over 15% improvement in
Added support for , , , , MOVBE, , , and
Up to four CPU cores
is shared between cores
datapath width increased to 128-bit
Added hardware integer divider
Enhanced cache
Doubled bandwidth of
C6 and CC6 low power states with lower entry and exit latency
Smaller, 3.1 mm2 area per core
Integrated
API Support
Special features
Core config
Pixel fillrate (/s)
Texture fillrate (/s)
Bus type & width
-width (/s)
November 2013
two modules with 4 cores each
2× 2 MB
OpenGL 4.2,
eight ACEs in the GPU and
November 2013
two modules with 4 cores each
2× 2 MB
Direct3D 11.2 and 12
two ACEs in the GPU
32 MB
two modules with 4 cores each
2× 2 MB
Direct3D 11.2 and 12
two ACEs in the GPU
32 MB
November 2016
2× 2 MB
OpenGL 4.2 (4.5),
Calculates 2 half-precision floats simultaneously
November 2017
two modules with 4 cores each
2× 2 MB
12 GB
Direct3D 11.2 and 12
 :  :
Precision performance is calculated from the base (or boost) core clock speed based on a
operation.
Pixel fillrate is calculated as the number of ROPs multiplied by the base (or boost) core clock speed.
Texture fillrate is calculated as the number of TMUs multiplied by the base (or boost) core clock speed.
Cores ( :
Athlon 5370
2.2 GHz
600 MHz
Athlon 5350
2.05 GHz
Athlon 5150
1.6 GHz
Sempron 3850
1.3 GHz
450 MHz
Sempron 2650
1.45 GHz
400 MHz
Max. Turbo
2.0 GHz
600 MHz
DDR3L-1600
1.55 GHz
500 MHz
1.5 GHz
500 MHz
1.65 GHz
450 MHz
1.4 GHz
400 MHz
DDR3L-1333
1.0 GHz
300 MHz
1.4 GHz
400 MHz
DDR3L-1066
DDR3L-1333
225 MHz
03.9 W
DDR3L-1066
Part number
2.0 GHz
OX1150IPJ44HM
Part number
1.9 GHz
OX2150IAJ44HM
2.4 GHz
September 2016
OX2170IXJ44JB
2.0 GHz
600 MHz
DDR3-1600 ECC
1.6 GHz
1.5 GHz
500 MHz
1.0 GHz
DDR3-1333 ECC
1.1 GHz
300 MHz
DDR3-1600 ECC
1.65 GHz
450 MHz
1.0 GHz
300 MHz
DDR3-1333 ECC
225 MHz
DDR3-1066 ECC
was released in 2014 and targeting entry level notebooks and tablets.
. AMD 2013.
. ExtremeTech. November 22, .
. SemiAccurate 2013.
. Bright Side Of News 2013.
. AMD 2013.
MACHKOVECH, SAM (2 August 2016). . Ars Technica 2016.
Walton, Mark (10 August 2016). . Ars Technica 2016.
Walton, Mark (19 April 2016). . Ars Technica 2016.
Smith, Ryan (8 September 2016). . Anandtech 2016.
Cutress, Ian (21 August 2017). . Anandtech 2017.
Freedman, Andrew (3 November 2017). . Tom's Guide 2017.
. AMD 2014.
. Tech News Pedia 2013.
Shimpi, Anand. . AnandTech 2013.
. Amd.com. .
. YouTube. .
Shvets, Gennadiy. . cpu-world.com. CPU-World 2015.
(PDF). AMD.
. deciso.com. Deciso B.V 2015.
Schellevis, Jos. . community.amd.com. Advanced Micro Devices, Inc 2015.
. pcengines.ch.
Lal Shimpi, Anand (29 April 2014). . Anandtech 2017.
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