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Hibernatus&()
The frozen body of Paul Fournier is discovered in Greenland where he had disappeared during a scientific expedition in 1905. Perfectly conserved he is brought back to life in the 1960s. His...
(adaptation)
, , , , , and director
reveal which
star had the cast in stitches during filming.
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Top-notch french restaurant owner Monsieur Septime is involved into crime when one of his famous guests disappears.
Jacques Besnard
Louis de Funès,
Bernard Blier,
Maria-Rosa Rodriguez
Based on Molière's play. The children of Harpagon, Cléante and his sister Elise, are each in love but they still haven't spoken to their father yet. Harpagon is a miser who wants to choose ...
Directors:
Louis de Funès,
Jean Girault
Louis de Funès,
Franck Cabot-David,
Hervé Bellon
Louis-Philippe Fourchaume, another typical lead-role for French comedy superstar Louis de Funès, is the dictatorial CEO of a French company which designs and produces sail yachts, and fires...
Robert Dhéry
Louis de Funès,
Andréa Parisy,
Franco Fabrizi
Don Salluste, a petty tyrant in his own home and minister of the King of Spain, falls from grace. Wanting revenge, he tries to compromize the Queen with his valet Blaze, introduced as his ...
Gérard Oury
Louis de Funès,
Yves Montand,
Alice Sapritch
Manager of female dance group and his cousin leads the group on a tour in the Rome and prohibit them to socialize with men. Problems occur when we see that one of the girls has a baby in Rome.
Serge Korber
Louis de Funès,
No?lle Adam,
Olivier De Funès
Neurotic businessman must find the right man for his pregnant daughter. In fact, it is little bit complicated.
?douard Molinaro
Louis de Funès,
Claude Rich,
Mario David
The whole clique of Cruchot's police station is retired. Now he lives with his rich wife in her castle - and is bored almost to death. He fights with the butler, because he isn't even ...
Jean Girault
Louis de Funès,
Jean Lefebvre,
Guy Grosso
The gendarme Cruchot meets the widow Josepha. They quickly fall in love but Cruchot's daughter doesn't like Josepha and is determined to prevent the wedding by all means necessary.
Jean Girault
Louis de Funès,
Jean Lefebvre,
Geneviève Grad
Antoine Brisebard, a famous comedy playwright, is struggling with financial difficulties and is preparing to sell his country villa to an English couple. What no one knows, however, is that...
Jean Girault
Louis de Funès,
Claude Gensac,
Michel Galabru
Guillaume has made it: A machine that can clean dirty air by simply sucking all dirt into air balloons and then shipping them far far away so his explanation. Some Japanese business guys, ...
Claude Zidi
Louis de Funès,
Annie Girardot,
Maurice Risch
Politician get hitch hikers on road and in one car accident they all end up on a tree above the sea.
Serge Korber
Louis de Funès,
Geraldine Chaplin,
Olivier De Funès
An art dealer wants to buy a Modigliani, which is tattooed on the back of an old soldier.
Denys de La Patellière
Jean Gabin,
Louis de Funès,
Paul Mercey
Cast overview, first billed only:
Hubert de Tartas
Le professeur ?douard Loriebat
(as Michel Lonsdale)
Edmée de Tartas
Paul Fournier
Mme Crépin-Jaujard, la mère d'Evelyne
Didier de Tartas
Evelyne Crépin-Jaujard
Le professeur Bibolini
Le secrétaire général
Crepin-Jaujard
L'assistante de Bibolini
Une infirmière
The frozen body of Paul Fournier is discovered in Greenland where he had disappeared during a scientific expedition in 1905. Perfectly conserved he is brought back to life in the 1960s. His descendants take care of him: to spare him the cultural shock they behave so to make believe it's 1905 and they are his cousins, uncle...
Written by
Plot Keywords:
Certificate:
Parents Guide:
Release Date: 10 September 1969 (France)
Also Known As: El abuelo congelado
Filming Locations:
Production Co:
Show detailed
Sound Mix:
(Eastmancolor)
Aspect Ratio: 2.35 : 1
Did You Know?
First feature film of .
Connections
Featured in &(2002)
Frequently Asked Questions
User Reviews
Same origin as modern Captain America (DVD)
De Funes movies have filled my childhood and "Hibernatus" didn't leave me a good memory. At the time, I couldn't stand the doctor (Londsale) and the "hibernatus". In addition, i felt stuck in the big old furnished mansion. Today, I find it rather enjoyable. The "hibernatus" really appears during the second half of the movie and the interview of the actor 30 years later available on the bonus helps soften his character. Moreover, De Funes steals the show as always and has the genius to turn "bad" guys into memorable characters.As I underlined in other reviews, a truly good comedy surprises you at each viewing because you can't remember all the funny moments. This is also the case here.In comparison with today movies, its short length (80 min) is appreciable because it's fast paced and has no time out.
1 of 8 people found this review helpful.&
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Create a character page for:
Hubert de Tartas
Le professeur ?douard Loriebat
Edmée de Tartas
Paul Fournier
Mme Crépin-Jaujard, la mère d'Evelyne
Didier de Tartas
Evelyne Crépin-Jaujard
Le professeur Bibolini
Le secrétaire général
Crepin-Jaujard
L'assistante de Bibolini
Une infirmière
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Follow IMDb onMethod and system for providing low density parity check (LDPC) encoding and decoding
United States Patent 8402341
An approach is provided for processing structure Low Density Parity Check (LDPC) codes. Memory storing edge information and a posteriori probability information associated with a structured parity check matrix used to generate Low Density Parity Check (LDPC) coded signal are accessed. The edge information represent relationship between bit nodes and check nodes, and are stored according to a predetermined scheme that permits concurrent retrieval of a set of the edge information.
Inventors:
Eroz, Mustafa (Germantown, MD, US)
Lee, Lin-nan (Potomac, MD, US)
Application Number:
Publication Date:
03/19/2013
Filing Date:
02/18/2010
Export Citation:
EROZ MUSTAFA
LEE LIN-NAN
Primary Class:
Other Classes:
International Classes:
H03M13/00; G06F11/00; G11C29/00; H03M13/03; H04L1/18
View Patent Images:
&&&&&&PDF help
US Patent References:
8291293Eroz et al.8181085Eroz et al.8145980Eroz et al.8144801Eroz et al.8140931Eroz et al.8102947Eroz et al.8095854Eroz et al.8069393Eroz et al.8028224Eroz et al.7962830Eroz et al.7954036Eroz et al.7864869Eroz et al.7856586Eroz et al.7770089Eroz et al.7725802Eroz et al.7673226Eroz et al.7577207Eroz et al.7483496Eroz et al.Sun et al.7461325Eroz et al.7430396Sun et al.7424662Eroz et al.714/7587398455Eroz et al.7376883Eroz et al.7334181Eroz et al.7296208Sun et al.7237174Eroz et al.7234098Eroz et al.Eroz et al.714/7527203887Eroz et al.7191378Eroz et al.714/7587020829Eroz et al.6963622Eroz et al.6829308Eroz et al.Eroz et al.714/800Eroz et al.
Primary Examiner:
Merant, Guerrier
Attorney, Agent or Firm:
Potomac Technology Law, LLC
What is claimed is:
A method comprising: accessing, by a processor of a device, memory storing information representing a predetermined structured parity check matrix of a Low Density Parity Check (LDPC) code for encoding information bits, the information representing the structured parity check matrix being organized in tabular form, wherein each row represents occurrences of one values within a respective column of the parity check matrix, wherein the columns of the parity check matrix are derived according to a predetermined operation based on the respective rows of the and encoding the information bits, and outputting an LDPC coded signal comprising the encoded information bits, wherein the LDPC code is of a structure that facilitates use of a plurality of parallel engines for decod wherein the encoding comprises: initializing parity bit
accumulating a first information bit in a jth group of M information bits in an ith parity bit accumulator if the ith entry in the (jM)th column of the parity check matrix is 1, where j=0, 1, 2, 3, . . . kldpc/M-1; accumulating the remaining (M-1) information bits m=jM+1, jM+2,jM+3, . . . (j+1)M-1 of the jth group in the parity bit accumulators according to {x+m mod M*q} mod(nldpc-kldpc), wherein x denotes an address of the parity bit accumulator corresponding to the first bit, jM, in the group, and q=(nldpc-kldpc)/M is a code rat and after all of the information bits are accumulated, performing operations, starting with i=1 according to pi=pi⊕pi-1, i=1, 2, . . . (nldpc-klpdc-1), wherein final content of pi, i=0, 1, . . . (nldpc-klpdc-1) is equal to the parity bit pi; wherein the tabular information representing the structured parity check matrix comprises a one of Tables 1 through 24 (below), wherein the row indices of 1's in the column index j*M (j=0, 1, 2, 3, . . . klpdc/M-1) of the parity check matrix are given at the jth row according to the one Table, and wherein kldpc is associated with a lengt TABLE 1Address of Parity Bit Accumulators (Rate
- Coded Block Size 720)83 117 156 169 231 126 112 106120 169 106 27 188 213 22 159160 121 106 203 196 141 174 13564 137 226 91 180 85 166 782 7 198 148134 24 9 83149 160 1 15174 203 116 13206 12 101200 45 9816 235 165167 25 1712 83 338 174 20736 170 20773 172 86 TABLE 2Address of Parity Bit Accumulators (Rate
- Coded Block Size 960)52 293 211 106 128 87 286 89224 273 74 99 28 301 142 311160 201 210 123 252 165 198 183296 105 10 283 244 317 302 263289 168 207 267167 170 141 156270 266 240 17189 28 237 158113 67 11866 160 22144 269 18053 59 12136 183 238171 140 314271 168 42153 173 31 TABLE 3Address of Parity Bit Accumulators (Rate
- Coded Block Size 1440)140 296 319 355 373 182 329 266144 169 426 155 348 381 78 87120 169 242 371 292 13 286 95280 449 10 371 396 405 78 15317 42 380 336254 233 301 60251 175 218 120465 147 390 407387 273 287120 279 97404 22 283323 256 453182 77 44990 20 48466 415 301474 228 350 TABLE 4Address of Parity Bit Accumulators (Rate
- Coded Block Size 2160)458 368 73 243 357 298 305 695375 511 575 629 186 130 624 561297 284 204 637 10 623 195 436300 433 110 712 401 618 379 608710 700 390 535 73 478 524 641456 554 363 400 174 463 249 575228 542 556 49330 684 581 225195 134 61 82461 45 387 24491 128 71 246439 212 274 359476 394 234171 501 391327 528 41186 62 253513 295 157661 152 19616 490 710239 257 96687 710 408525 160 18671 331 370101 68 695 TABLE 5Address of Parity Bit Accumulators (Rate
- Coded Block Size 2880)689 581 139 306 45 371 886 576864 596 6 651 693 810 770 281270 557 325 275 561 672 196 22620 324 77 312 851 642 917 480375 88 57 746 364 910 527 644753 823 360 921 218 411 908 190327 111 217 269 888 307 914 934785 439 682 171 60 686 959 30879 103 568 563337 312 523 352906 492 471 800250 867 303 860287 619 702 706262 430 9 941293 225 244 626629 918 697 381145 371 102597 575 280464 618 388509 844 631525 123 362611 638 27126 433 548485 745 726561 742 125754 318 457864 219 632354 688 116523 425 552935 147 735956 807 610421 60 142 TABLE 6Address of Parity Bit Accumulators (Rate
- Coded Block Size 3600)157 563 346 756 65 524 238 859133 475
858 76 301284 200 701 389 119 8812 853 194 459 500 415 346 448381 418 343
87 169402 105 410 511 534 417 676 883762 170 553 957 559 618 276 412 505 486 607 308 389 110 251 871 69 2760 445 906 167 68 792 573 254684 999 752 981442 651 372 1113366 204 230 25 768909 61 798 10369 60 174 16759 915 728 356655 456 997 96737 755 113 1045142 443 934 297930 597 452 760439 725 889377 511 752330 817 1155239 522 725 95871 813 3092 539 1164504 545 707141 714 38923 874 369623 904 541340 756 382273 661 1195194 29 9317326 18 927246 488 976 TABLE 7Address of Parity Bit Accumulators (Rate
- Coded Block Size 4320)3 574 702 78 6 88 924914 633 5 924
48113 4 102 337 695 504348 286 209 712 85 207 748 1340653 203
307 455 982 917 355 165 527 513 36 655 86 530313 556 630 1 904 66644 487 166 565 335 521 699 27201 630 10 59 326 639601 42107 74469 525 588 827 2093 1037960 992 129 13975 1167244 427 44 560 88 787362 565 688 13652 674727 802 296 801 1209800 776 478 1249291 178 1375375 385 682744 187 1343178 371 41532688 873 494295 122 733 137572 981 589672 534 417 277268 461 335 97 3 TABLE 8Address of Parity Bit Accumulators (Rate
- Coded Block Size 5760)956 226 8 767 474 759199 742 0 426 300
37602 658 545 6 131 2838 525 7 5947 86
184171 800 875 102 928 79154 29 910 139315 709
126217 869 769 661 703 10255 7 590 333259 246 2 551 501 778
05 176 731 704 4 276 247 30612 6695 2 200454 926 349 17472 1060 386 705556 3 80151 4 477 310 13811 103 1139711 221 1575515513 165 1911320 822 1469518 662 679 65737 883 1030642 138 20297 238 971 14278447 398 997 1467580 354 1388236 418 1011110 656 1583849 1756 8954942 99 92634 226 1559 TABLE 9Address of Parity Bit Accumulators (Rate
- Coded Block Size 720)75 126 40 130 137 104108 132 7 70 35 9581 57 97 40 20 12563 142 128117 73 11021 85 12563 100 83120 142 1340 94 113141 24 70 94 20 14396 30 43 1 47 10439 123 13 31 89 65 TABLE 10Address of Parity Bit Accumulators (Rate
- Coded Block Size 960)90 169 14 33 76 59108 127 8 177 154 119126 85 116 63 142 11108 1 86 117 184 191174 37 44 159 124 2336 73 20 147 28 4176 54 47147 142 121176 163 41170 52 1156 135 12218 105 113159 26 15595 62 16324 83 7166 135 18766 22 62186 39 5890 67 110 39 178 1076 163 104 159 16 7148 145 98 63 76 173102 25 104 177 160 155150 7 110 189 124 113144 25 80 117 22 71 TABLE 11Address of Parity Bit Accumulators (Rate
- Coded Block Size 1440)264 211 242 129 16 11948 205 80 63 244 263216 157 266 117 34 23138 157 62 69 184 19154 271 242 255 88 27584 145 128 219 268 89127 262 59148 60 12280 24 6127 250 1175 18 103278 147 563 224 95201 7 56213 217 28642 8 19042 23 15442 73 14384 109 86 63 262 233126 19 110 207 262 149210 121 248 279 4 227264 217 176 99 268 113108 103 284 225 262 1742 205 14 129 262 5 TABLE 12Address of Parity Bit Accumulators (Rate
- Coded Block Size 2160)281 315 114 116 176 342362 150 317 33 131 280431 137 422 154 68 17653 391 168 258 17 139188 69 199 0 57 38219 108 429 335 414 385234 323 180 309 39 56162 3 340 189 214 359408 9 30221 305 174341 208 410202 272 267378 165 3954 383 377228 15 35356 86 22379 225 19491 314 254366 393 251338 181 42579 29 15284 72 125372 63 25643 204 422390 59 200 429 351 265408 118 106 173 68 30516 233 390 415 219 244106 251 428 70 311 21682 413 59 342 337 76114 357 215 352 174 425138 83 12 373 287 241 50 203 252 85 239 TABLE 13Address of Parity Bit Accumulators (Rate
- Coded Block Size 2880)111 270 437 502 215 181115 18 330 442 508 57201 182 392 492 206 124189 451 399 501 403 32200 229 331 351 294 55263 94 539 298 378 475362 562 320 395 357 540452 399 202 419 449 393541 128 462 256 527 206165 533 46529 163 494388 102 474361 183 11355 539 34769 565 162160 473 76432 508 35117 527 385556 514 422556 289 534385 572 366 303 1429 364 51495 58 41190 209 222279 188 292459 182 35947 64 413 399 402 27563 35 345 454 32 353317 307 34 440 315 11245 191 352 60 120 151290 192 503 509 474 52490 313 123 299 206 345198 370 265 221 363 7558 496 166 185 132 8351 424 436 527 96 430 TABLE 14Address of Parity Bit Accumulators (Rate
- Coded Block Size 3600)76 283 600 479 262 505293 236 203 12 711 181666 76 24 687 283 527339 302 389 571 618 65938 469 340 151 555 34248 637 466 352 497 571429 706 259 96 459 378297 40 656 282 119 682506 573 228 649 329 70238 272 81 305 138 15462 632 93 267 563 172336 133 650 557 692 309358 271 456263 435 533655 660 29356 115 160692 100 396313 435 57267 16 575370 383 398554 524 221210 517 585438 157 10170 522 333611 426 28423 185 78141 196 60217 558 250420 485 668351 166 129576 309 235146 339 348379 604 23313 319 694601 188 611697 446 46470 460 23 530 342 627661 268 10 434 300 3612 376 351 150 29 287503 15 326 25 257 680359 29 342 391 214 108223 25 131 162 458 29693 594 574 48 524 343645 375 106 479 678 40892 213 691 88 204 221109 92 165 226 52 698697 415 704 309 496 158361 315 689 427 572 513 TABLE 15Address of Parity Bit Accumulators (Rate
- Coded Block Size 4320)67 837 44 354 141 632292 816 309 137 515 334709 598 186 77 169 430398 551 661 99 329 15752 230 687 837 554 57308 303 181 138 190 512646 202 184 382 535 143440 281 158 673 434 518329 561 164 854 712 41145 470 274 759 90 33150 273 858 732 447 455835 257 816 72 415 251444 609 690 263 388 3299 44 189 403 484 567592 331 252 621 721 626688 324 456 251 44 765529 783 541290 560 542447 792 530365 753 436356 161 445402 805 278852 799 149376 599 10155 240 5243 331 86235 140 184752 811 202425 444 679606 731 326105 234 35598 585 810118 175 145255 506 80662 825 464585 594 45127 581 567430 722 179391 195 228206 165 381760 480 423774 748 18526 337 720746 189 689636 120 676306 831 40267 124 301148 485 219428 157 595 505 575 282598 201 151 484 627 96551 148 169 184 845 611513 688 585 371 855 414734 139 696 404 252 341496 577 149 164 339 285238 827 336 339 631 38533 738 641 633 463 36519 767 641 624 748 585421 848 385 356 747 376732 222 490 200 406 65845 410 498 286 135 655502 152 78 273 13 75546 122 357 550 120 571514 362 572 479 155 358642 389 90 220 749 591 TABLE 16Address of Parity Bit Accumulators (Rate
- Coded Block Size 5760)389
59 92196 260 661 696 74 1098375 444 435 540 1 5429 673
797 780 161 190 661 883 745620 594 79 742 441 435838 59 501 129 403 117 110 67 65444
885 513 563 757 927690 835 0 651742 587 230 170 748 132688 3 6 16886 29 14 593 20 998540 904 605 932 882
976 629 194799 762 578577 96 66203 751 141365 269 201549 25 880217 336 788146 664 849893 498 1119862 490 978727 203 717162 946 1131332 982 325661 604 868764 36 774 746 623384 774 381 889627 261 73147 97 1045621 693 734 291160 932 427994 619 848923 431 318935 887 1059970 984 730696 21 418266 684 96358 797 717602 877 325184 782 6254 562 566 715 198 975 365 519268
287 47813 419 213 575 842 748918 363 549 644 188 128 508 828 8443 44 426 580200 858 241 89 119 294305 64 560 284 675 847925 916 740 18 90 669 470 509 937 514 852 792 51 780
676 739802 963
173619 44 844 977 384 249687 727 81 300 448 636867
TABLE 17Address of Parity Bit Accumulators (Rate
Coded Block Size 720)207 174 209 139 68 88270 136 45 188 329 14513 335 136 6 213 20161 74 339 30730 262 39 212282 19 124 275 TABLE 18Address of Parity Bit Accumulators (Rate
- Coded Block Size 960)424 467 351 278 130 273138 208 267 420 457 470387 230 264 237 68 346450 148 62 67 5 225213 471 123 289159 412 221 434136 479 246 148448 65 213 239 TABLE 19Address of Parity Bit Accumulators (Rate
- Coded Block Size 1440)414 469 23 658 559 44013 322 153 338 220 539567 661 680 386 259 347207 511 215 469 536 42083 295 133 280 363 378713 453 579 307 234 676148 471 150 633509 417 524 696681 360 306 281674 130 544 629252 326 10 46172 122 488 562 TABLE 20Address of Parity Bit Accumulators (Rate
- Coded Block Size 2160)297 811 822 736 708 943786 553 17 33 889 4966 681 597 911911 71 753 446 49 854717
228 1116 572 295 736 517 419164 80 651 937 221 845 537 472 934 172 787 1270 784 605 590766 5 50 426316 146 664 581929 722 251 201324 184 193 60436 81 412 342867 688 819 1141 453 688 63 TABLE 21Address of Parity Bit Accumulators (Rate
- Coded Block Size 2880)101
236 1044486
845 573 140 278 717646 922
231 41 622 392 300 526 196 138748 4 875 552 728 175 826 111708 469 262 501 570 5 7128 836 781 323 1360720 712 36 13885 457689 115 537 995 1 105871 8 83259 785365 819 954 523 781795 401 210 1171 TABLE 22Address of Parity Bit Accumulators (Rate
- Coded Block Size 3600)3 653 1242 3 270
831 5 93667 278 947 473 193 10388 80 78130 323 181 64 8175 133 250 369 6 34 682330 113 4 860897 270
8583 9681 864 0 63889 11108 779 16691 1229434 154 515 1321374 620 321 839 962 1507921 165
30952 8972 929 176 832 7 3666 417 TABLE 23Address of Parity Bit Accumulators (Rate
- Coded Block Size 4320)175 41 262 03 875 522 8969 346 198 451 367 43 601 674 13526 191 383 2007140 562 75 1162879 708 609 37 4 22169 312 386 7 821 569 33 94 915 25 9116 5 745 56 396 64 9 1290 13837 18 13528 588 6 83597 699489 590 980 12 449 0 1316 91002 2053773 728 938 8697 14172 293900 6 TABLE 24Address of Parity Bit Accumulators (Rate
- Coded Block Size 5760)991 3 234 760883
17 477 646 9 273710 14 120 22345 954 44 4 135026 7 177 2031567 48 678
8 696 976 7 2 660 296 980 313956
707 853 295 179 16027 5117 7 198 7
17 17 701 454 7
44 175 838 445126
1463911 45 27614 19461 34761 4506 261818 25920 211247 829 814 28351 510 8 170328 23076 1991 159680 22111 1740 62852 332.
A method according to claim 1, further comprising: modulating the LDPC coded signal according to a signal constellation that includes one of OQPSK (Offset Quadrature Amplitude Modulation), QPSK (Quadrature Phase Shift Keying), 8-PSK (Phase Shift Keying), and 16-APSK (Amplitude Phase Shift Keying).
A method comprising: accessing, by a processor of a device, memory storing information representing a predetermined structured parity check matrix of a Low Density Parity Check (LDPC) code for encoding information bits, the information representing the structured parity check matrix being organized in tabular form, wherein each row represents occurrences of one values within a respective column of the parity check matrix, wherein the columns of the parity check matrix are derived according to a predetermined operation based on the respective rows of the and encoding the information bits, and outputting an LDPC coded signal comprising the encoded information bits, wherein the encoding comprises: initializing parity bit accumulators to zero, accumulating a first information bit in a jth group of M information bits in an ith parity bit accumulator if the ith entry in the (jM)th column of the parity check matrix is 1, where j=0, 1, 2, 3, . . . kldpc/M-1, accumulating the remaining (M-1) information bits m=jM+1, jM+2,jM+3, . . . (j+1)M-1 of the jth group in the parity bit accumulators according to {x+m mod M*q} mod(nldpc-kldpc), wherein x denotes the address of the parity bit accumulator corresponding to the first bit, jM, in the group, and after all of the information bits are exhausted, performing operations, starting with i=1 according to pM=pM⊕p0 p2M=p2M⊕pM p3M=p3M⊕p2M ??? pnldpc-kldpc-M=pnldpc-kldpc-M⊕pnldpc-kldpc-2M p1=p1⊕pnldpc-kldpc-M pM+1=pM+1⊕p1 p2M+1=p2M+1⊕pM+1 ??? pnldpc-kldpc-M+1=pnldpc-kldpc-M+1⊕pnldpc-kldpc-2M+1 p2=p2⊕pnldpc-kldpc-M+1 pM+2=pM+2⊕p2 p2M+2=p2M+2⊕pM+2 ??? pnldpc-kldpc-M+2=pnldpc-kldpc-M+2⊕pnldpc-kldpc-2M+2 p3=p3⊕pnldpc-kldpc-M+2 pM+3=pM+3⊕p3 p2M+3=p2M+3⊕pM+3 ??? pnldpc-kldpc-M+3=pnldpc-kldpc-M+3⊕pnldpc-kldpc-2M+3 ????? pM-1=pM-1⊕pnldpc-kldpc-2 p2M-1=p2M-1⊕pM-1 P3M-1=p3M-1⊕p2M-1 ??? pnldpc-kldpc-1=pnldpc-kldpc-1⊕pnldpc-kldpc-M-1 wherein final content of pi, i=0, 1, . . . (nldpc-kldpc-1) is equal to the parity bit pi.
A method according to claim 3, wherein M=360.
A method according to claim 4, wherein coded block size nldpc is 64800 code rates are 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10, respectively.
A method according to claim 3, wherein the tabular information representing the structured parity check matrix comprises a one of Tables 25 through 35 (below), wherein the row indices of 1's in the column index j*M, (j=0, 1, 2, 3, . . . kldpc/360-1) of the parity check matrix are given at the jth row according to the one Table, and wherein kldpc is associated with a lengt TABLE 25Address of Parity Bit Accumulators (Rate 9/10 - Coded Block Size 64800)853 1589 5634956 2662 6167739 4765 627045 5151860 11369 46122 16262 9333 3244540 5363 5842126 535 450 1049 5772234 321803233 447 2661407 915364753 882 476 145884 94160 26219682340 278 154 585206765 23176329429 741 2271419 595 855 7946875 305 22473 86 433 6038771 60151 584 361071558330239550269 604 191871247 788 180926796 406 812 3768259699271 360 4695216651601319550 415 8270192727010648813 39517 0 23274 745 4778319 807 462521296 607 66331896586073162 871 213571 32367 104603459 229 197 671 2247427037382 815 84122047362 5525305 96796 958 021645 12501990129 6442457 81160 659 2182641 4507853 966
TABLE 26Address of Parity Bit Accumulators (Rate 8/9 - Coded Block Size 64800)71 539561 651909 602483 708887 701017 527462 396101 6537309 60126 09300 558 18 641923 66350 24582 11957 1455 4994998 66519 24534 873 578 945 21 670368 62354 67350 96396 3418 695368 464562 3781840 3563 695930 6336180 1195 5046371 949 712 6339 617429 618046 552442 7165523 7499 5006450 754 61 7120 7067872 6059 628473 598193 447659 408168 559562 19248 650 04 56426 3732 699580 681599 635132 6942562 65311 112 530 756076975 9191717 02852 081374212 923 6113370 942579 550 15829995827 325 61990241202 719 544984459 742 976 594880358859340 488 17023430 579 785 386928785 971 597 299 751259625006782010352 655 950 98367 229620317 2295351328961 62233 800 88585 58112 110 3611210 459 15630866586 18289655557172620 768 60581532876
TABLE 27Address of Parity Bit Accumulators (Rate
- Coded Block Size 64800)214 03 94 96 67 6944 89 5061 27 65992 53 83 53 82 61 549 60 34 435 93 84 24 90 1132 52 00 501 82 19 556 00 89 30 98
10643188 65 15 265 57 98 236 96 34 529 16 97 43 922 36 196 10528692 46 62 632 50 88 4 936 54 86 814118 424 17 68 943608 67 00848 68 40899 23
10647741 93 56 54 57 10376 908 31 83 8778987 43 57 966 73 74 47908316386342 786230 46699 627 747 4057360 428 101192027167745 83880 502099846622766214 24875314857575278 277 2984571732243823 783 32792509810 637 5827184702 692 14958 2815875110992 1450676832656 3005611901968 0828323 607 1070183 352 408655 13307788739 58211 788 106940645538619 577 5095471029248 768 017618890 77605558271530428 324094418 TABLE 28Address of Parity Bit Accumulators (Rate
- Coded Block Size 64800)88 40
1293689 71 12
37 58 850 95 91 93 706 11883476 913 79 67
12888468 74 29 577 1272863 955 13 88
1239819 11
1265380 41 86
437 982 71 377
1226002 28 533 46 81 79 96 11775188 24 01
346 668 925 20 570 13 97 52 72 74
11823980 15 58
58 80 12 69640 42259375 998 807 3000558022195570698 44150524081699123 1194816253704451939331 623 50474 871009 10869856 05775796830 855747 7093124401602153 663669771329 409 976 57876 311964975813435769756132 1178785399 928981333 55929708771 129062916552594028143 136 715 477925900611 51862 11971 11718 12924543368238834242 75 12906412 12664497523 01498 19871 642684095530335437640 306527091 595292 70 TABLE 29Address of Parity Bit Accumulators (Rate
- Coded Block Size 64800)89
257 55 43 50 70 65 02
11606 92 93
12136 53 07
10825 891 09 97 12 625 83 26
12574 91 58 463 12994 358 594 55 328
860 68 22 52498
12022546 15688 12643284468413661 811 159 14909 1343416089 14377153 687 859701 1480196702 30 1585803186243323 12635 1497128659622 1589255368842835878623 13847244 12890 1313241
13846 16119 15794461426050 15695791655 660810 13767725 14604878993303 20309984935115 188648 602 988 44972 807 931 15238 15553 15637 130407 767054541 231557096663 417 16104939279717 734 91 15553 1190032699
13789366054 1343679875380306 956929856599247671942949
1101568 TABLE 30Address of Parity Bit Accumulators (Rate
- Coded Block Size 64800)186
29 496 2093245
54 788 19387257
30 108 1651755
603 53 80022
20934200 68
40345937083 20123404823
18118 19524 11405493
16865344 17544 18443 20689 14306 15930 14361 19136672 20412 20284314 718870180 334186
21593116 17920226 18444 21397 14678118 735584 20027 21258 2121964 11712 16156 16655 177063251856 18850874876 14312 19036 20068938
15341 18913 17541 12365396 070 15008 19548 20525697 20406 20942 13410152
17236216 54085 21560 2104710365709 177961900
19778 12317 20332 18027644 595005 TABLE 31Address of Parity Bit Accumulators (Rate
- Coded Block Size 64800)
1995775 53
57 646 467
24267902 30
22010939 512
2255027 970 541 924 37
21840378 80
588 857 13 54 12848 24447 22074082564 24211341 323
22658 13320289 533
2002875 21282 24968665602 20657 24693 23813 21530 23406 25283 12236 21017 25712353 15312495 15270 25869 2206992553 25599591673386 20518644 20440 18267 19917 24520 15040144 13867 22746628
18998719729 20091849 21754 22399893
17456 24063488 757 16932 23973 24978782
23080 15669 17284 23285 TABLE 32Address of Parity Bit Accumulators (Rate
- Coded Block Size 64800)
30963347 71
31413876 22
2357490 792
15275303 27550 20167329
30914 26143 29562423 31855250 21323 29095 32396 30015 25755 30378259 24705854078 25612 29625 20819541 27847249 30933 29543 30687 2086357 25761 19685 20662 19410 32037793
2320134987 24186 28552 25266 23870754 21285221 28651619
30849 32018271612
25651 23874 26533454
31936 20152 TABLE 33Address of Parity Bit Accumulators (Rate
- Coded Block Size 64800)62
14180 30469494 37078 29341 21979026 37489253 38608 25368466 35696 19353442 838 26339 38759 14717 38419 38114 21066731 632 17631 34050747 36329 22488 36004 32363 14033 31025 38569 21031 34436 28666 30092837399
36108 27403 23361 33457 20421 32359 30059 31348 32657 TABLE 34Address of Parity Bit Accumulators (Rate
- Coded Block Size 64800)37
42394467 535
976 64 5589
35811 34952411 41783 35897 36715 41196 34976 32912 29630 32046 32622 37743 18132 29644 36470 20405 23944 32227 32862 34431 37568 21514 28406 38951 41428 33758 39284 41788 41111 33923 36184 40480 27939 41661 24200 42660331 31360 19794 TABLE 35Address of Parity Bit Accumulators (Rate
- Coded Block Size 64800)407 004
47137572 90
31419 67 19 009 14190
35152 38708 42413 27784 48159 38594 34900 24603 27441 43211210
31602 29610 37802606 47221 44496 42727 47800 43721686 47500 44968 43948429 45622 47703 44970 45392 44279 45118 45091.
A method according to claim 3, further comprising: encoding an input signal according to Bose Chaudhuri Hocquenghem (BCH) codes, wherein the output LDPC coded signal corresponding to the input signal represents a code having an outer BCH code and an inner LDPC code.
A method according to claim 7, wherein the number of redundant BCH bits is nBCH-kBCH=192 and error correction capability of the BCH code is 12 bits.
A method according to claim 3, further comprising: interleaving the output LDPC coded signal
and modulating the interleaved LDPC coded signal based on 8-PSK (Phase Shift Keying) or 16-APSK (Amplitude Phase Shift Keying) modulation scheme, wherein the interleaving comprises writing the LDPC coded signal into the interleaver column-wise and reading an interleaved output LDPC coded signal row-wise, from left to right, and wherein if an 8-PSK modulation scheme is used for a code rate 3/5, the interleaved output LDPC coded signal is read from right to left.
An apparatus comprising: memory configured to store information representing a predetermined structured parity check matrix of a Low Density Parity Check (LDPC) code for encoding information bits, the information representing the structured parity check matrix being organized in tabular form, wherein each row represents occurrences of one values within a respective column of the parity check matrix, wherein the columns of the parity check matrix are derived according to a predetermined operation based on the respective rows of the an encoder configured to encode the information bits, and to output an LDPC coded signal comprising the encoded information bits, wherein the LDPC code is of a structure that facilitates use of a plurality of parallel engines for decod wherein the encoding comprises: initializing parity bit
accumulating a first information bit in a jth group of M information bits in an ith parity bit accumulator if the ith entry in the (jM)th column of the parity check matrix is 1, where j=0, 1, 2, 3, . . . kldpc/M-1; accumulating the remaining (M-1) information bits m=jM+1, jM+2,jM+3, . . . (j+1)M-1 of the jth group in the parity bit accumulators according to {x+m mod M*q} mod(nldpc-kldpc), wherein x denotes an address of the parity bit accumulator corresponding to the first bit, jM, in the group, and q=(nldpc-kldpc)/M is a code rat and after all of the information bits are accumulated, performing operations, starting with i=1 according to pi=pi⊕pi-1, i=1, 2, . . . (nldpc-kldpc-1), wherein final content of pi, i=0, 1, . . . (nldpc-kldpc-1) is equal to the parity bit pi; wherein the tabular information representing the structured parity check matrix comprises a one of Tables 1 through 24 (below), wherein the row indices of 1's in the column index j*M (j=0, 1, 2, 3, . . . klpdc/M-1) of the parity check matrix are given at the jth row according to the one Table, and wherein kldpc is associated with a lengt TABLE 1Address of Parity Bit Accumulators (Rate
- Coded Block Size 720)83 117 156 169 231 126 112 106120 169 106 27 188 213 22 159160 121 106 203 196 141 174 13564 137 226 91 180 85 166 782 7 198 148134 24 9 83149 160 1 15174 203 116 13206 12 101200 45 9816 235 165167 25 1712 83 338 174 20736 170 20773 172 86 TABLE 2Address of Parity Bit Accumulators (Rate
- Coded Block Size 960)52 293 211 106 128 87 286 89224 273 74 99 28 301 142 311160 201 210 123 252 165 198 183296 105 10 283 244 317 302 263289 168 207 267167 170 141 156270 266 240 17189 28 237 158113 67 11866 160 22144 269 18053 59 12136 183 238171 140 314271 168 42153 173 31 TABLE 3Address of Parity Bit Accumulators (Rate
- Coded Block Size 1440)140 296 319 355 373 182 329 266144 169 426 155 348 381 78 87120 169 242 371 292 13 286 95280 449 10 371 396 405 78 15317 42 380 336254 233 301 60251 175 218 120465 147 390 407387 273 287120 279 97404 22 283323 256 453182 77 44990 20 48466 415 301474 228 350 TABLE 4Address of Parity Bit Accumulators (Rate
- Coded Block Size 2160)458 368 73 243 357 298 305 695375 511 575 629 186 130 624 561297 284 204 637 10 623 195 436300 433 110 712 401 618 379 608710 700 390 535 73 478 524 641456 554 363 400 174 463 249 575228 542 556 49330 684 581 225195 134 61 82461 45 387 24491 128 71 246439 212 274 359476 394 234171 501 391327 528 41186 62 253513 295 157661 152 19616 490 710239 257 96687 710 408525 160 18671 331 370101 68 695 TABLE 5Address of Parity Bit Accumulators (Rate
- Coded Block Size 2880)689 581 139 306 45 371 886 576864 596 6 651 693 810 770 281270 557 325 275 561 672 196 22620 324 77 312 851 642 917 480375 88 57 746 364 910 527 644753 823 360 921 218 411 908 190327 111 217 269 888 307 914 934785 439 682 171 60 686 959 30879 103 568 563337 312 523 352906 492 471 800250 867 303 860287 619 702 706262 430 9 941293 225 244 626629 918 697 381145 371 102597 575 280464 618 388509 844 631525 123 362611 638 27126 433 548485 745 726561 742 125754 318 457864 219 632354 688 116523 425 552935 147 735956 807 610421 60 142 TABLE 6Address of Parity Bit Accumulators (Rate
- Coded Block Size 3600)157 563 346 756 65 524 238 859133 475
858 76 301284 200 701 389 119 8812 853 194 459 500 415 346 448381 418 343
87 169402 105 410 511 534 417 676 883762 170 553 957 559 618 276 412 505 486 607 308 389 110 251 871 69 2760 445 906 167 68 792 573 254684 999 752 981442 651 372 1113366 204 230 25 768909 61 798 10369 60 174 16759 915 728 356655 456 997 96737 755 113 1045142 443 934 297930 597 452 760439 725 889377 511 752330 817 1155239 522 725 95871 813 3092 539 1164504 545 707141 714 38923 874 369623 904 541340 756 382273 661 1195194 29 9317326 18 927246 488 976 TABLE 7Address of Parity Bit Accumulators (Rate
- Coded Block Size 4320)3 574 702 78 6 88 924914 633 5 924
48113 4 102 337 695 504348 286 209 712 85 207 748 1340653 203
307 455 982 917 355 165 527 513 36 655 86 530313 556 630 1 904 66644 487 166 565 335 521 699 27201 630 10 59 326 639601 42107 74469 525 588 827 2093 1037960 992 129 13975 1167244 427 44 560 88 787362 565 688 13652 674727 802 296 801 1209800 776 478 1249291 178 1375375 385 682744 187 1343178 371 41532688 873 494295 122 733 137572 981 589672 534 417 277268 461 335 97 3 TABLE 8Address of Parity Bit Accumulators (Rate
- Coded Block Size 5760)956 226 8 767 474 759199 742 0 426 300
37602 658 545 6 131 2838 525 7 5947 86
184171 800 875 102 928 79154 29 910 139315 709
126217 869 769 661 703 10255 7 590 333259 246 2 551 501 778
05 176 731 704 4 276 247 30612 6695 2 200454 926 349 17472 1060 386 705556 3 80151 4 477 310 13811 103 1139711 221 1575515513 165 1911320 822 1469518 662 679 65737 883 1030642 138 20297 238 971 14278447 398 997 1467580 354 1388236 418 1011110 656 1583849 1756 8954942 99 92634 226 1559 TABLE 9Address of Parity Bit Accumulators (Rate
- Coded Block Size 720)75 126 40 130 137 104108 132 7 70 35 9581 57 97 40 20 12563 142 128117 73 11021 85 12563 100 83120 142 1340 94 113141 24 70 94 20 14396 30 43 1 47 10439 123 13 31 89 65 TABLE 10Address of Parity Bit Accumulators (Rate
- Coded Block Size 960)90 169 14 33 76 59108 127 8 177 154 119126 85 116 63 142 11108 1 86 117 184 191174 37 44 159 124 2336 73 20 147 28 4176 54 47147 142 121176 163 41170 52 1156 135 12218 105 113159 26 15595 62 16324 83 7166 135 18766 22 62186 39 5890 67 110 39 178 1076 163 104 159 16 7148 145 98 63 76 173102 25 104 177 160 155150 7 110 189 124 113144 25 80 117 22 71 TABLE 11Address of Parity Bit Accumulators (Rate
- Coded Block Size 1440)264 211 242 129 16 11948 205 80 63 244 263216 157 266 117 34 23138 157 62 69 184 19154 271 242 255 88 27584 145 128 219 268 89127 262 59148 60 12280 24 6127 250 1175 18 103278 147 563 224 95201 7 56213 217 28642 8 19042 23 15442 73 14384 109 86 63 262 233126 19 110 207 262 149210 121 248 279 4 227264 217 176 99 268 113108 103 284 225 262 1742 205 14 129 262 5 TABLE 12Address of Parity Bit Accumulators (Rate
- Coded Block Size 2160)281 315 114 116 176 342362 150 317 33 131 280431 137 422 154 68 17653 391 168 258 17 139188 69 199 0 57 38219 108 429 335 414 385234 323 180 309 39 56162 3 340 189 214 359408 9 30221 305 174341 208 410202 272 267378 165 3954 383 377228 15 35356 86 22379 225 19491 314 254366 393 251338 181 42579 29 15284 72 125372 63 25643 204 422390 59 200 429 351 265408 118 106 173 68 30516 233 390 415 219 244106 251 428 70 311 21682 413 59 342 337 76114 357 215 352 174 425138 83 12 373 287 241 50 203 252 85 239 TABLE 13Address of Parity Bit Accumulators (Rate
- Coded Block Size 2880)111 270 437 502 215 181115 18 330 442 508 57201 182 392 492 206 124189 451 399 501 403 32200 229 331 351 294 55263 94 539 298 378 475362 562 320 395 357 540452 399 202 419 449 393541 128 462 256 527 206165 533 46529 163 494388 102 474361 183 11355 539 34769 565 162160 473 76432 508 35117 527 385556 514 422556 289 534385 572 366 303 1429 364 51495 58 41190 209 222279 188 292459 182 35947 64 413 399 402 27563 35 345 454 32 353317 307 34 440 315 11245 191 352 60 120 151290 192 503 509 474 52490 313 123 299 206 345198 370 265 221 363 7558 496 166 185 132 8351 424 436 527 96 430 TABLE 14Address of Parity Bit Accumulators (Rate
- Coded Block Size 3600)76 283 600 479 262 505293 236 203 12 711 181666 76 24 687 283 527339 302 389 571 618 65938 469 340 151 555 34248 637 466 352 497 571429 706 259 96 459 378297 40 656 282 119 682506 573 228 649 329 70238 272 81 305 138 15462 632 93 267 563 172336 133 650 557 692 309358 271 456263 435 533655 660 29356 115 160692 100 396313 435 57267 16 575370 383 398554 524 221210 517 585438 157 10170 522 333611 426 28423 185 78141 196 60217 558 250420 485 668351 166 129576 309 235146 339 348379 604 23313 319 694601 188 611697 446 46470 460 23 530 342 627661 268 10 434 300 3612 376 351 150 29 287503 15 326 25 257 680359 29 342 391 214 108223 25 131 162 458 29693 594 574 48 524 343645 375 106 479 678 40892 213 691 88 204 221109 92 165 226 52 698697 415 704 309 496 158361 315 689 427 572 513 TABLE 15Address of Parity Bit Accumulators (Rate
- Coded Block Size 4320)67 837 44 354 141 632292 816 309 137 515 334709 598 186 77 169 430398 551 661 99 329 15752 230 687 837 554 57308 303 181 138 190 512646 202 184 382 535 143440 281 158 673 434 518329 561 164 854 712 41145 470 274 759 90 33150 273 858 732 447 455835 257 816 72 415 251444 609 690 263 388 3299 44 189 403 484 567592 331 252 621 721 626688 324 456 251 44 765529 783 541290 560 542447 792 530365 753 436356 161 445402 805 278852 799 149376 599 10155 240 5243 331 86235 140 184752 811 202425 444 679606 731 326105 234 35598 585 810118 175 145255 506 80662 825 464585 594 45127 581 567430 722 179391 195 228206 165 381760 480 423774 748 18526 337 720746 189 689636 120 676306 831 40267 124 301148 485 219428 157 595 505 575 282598 201 151 484 627 96551 148 169 184 845 611513 688 585 371 855 414734 139 696 404 252 341496 577 149 164 339 285238 827 336 339 631 38533 738 641 633 463 36519 767 641 624 748 585421 848 385 356 747 376732 222 490 200 406 65845 410 498 286 135 655502 152 78 273 13 75546 122 357 550 120 571514 362 572 479 155 358642 389 90 220 749 591 TABLE 16Address of Parity Bit Accumulators (Rate
- Coded Block Size 5760)389
59 92196 260 661 696 74 1098375 444 435 540 1 5429 673
797 780 161 190 661 883 745620 594 79 742 441 435838 59 501 129 403 117 110 67 65444
885 513 563 757 927690 835 0 651742 587 230 170 748 132688 3 6 16886 29 14 593 20 998540 904 605 932 882
976 629 194799 762 578577 96 66203 751 141365 269 201549 25 880217 336 788146 664 849893 498 1119862 490 978727 203 717162 946 1131332 982 325661 604 868764 36 774 746 623384 774 381 889627 261 73147 97 1045621 693 734 291160 932 427994 619 848923 431 318935 887 1059970 984 730696 21 418266 684 96358 797 717602 877 325184 782 6254 562 566 715 198 975 365 519268
287 47813 419 213 575 842 748918 363 549 644 188 128 508 828 8443 44 426 580200 858 241 89 119 294305 64 560 284 675 847925 916 740 18 90 669 470 509 937 514 852 792 51 780
676 739802 963
173619 44 844 977 384 249687 727 81 300 448 636867
TABLE 17Address of Parity Bit Accumulators (Rate
- Coded Block Size 720)207 174 209 139 68 88270 136 45 188 329 14513 335 136 6 213 20161 74 339 30730 262 39 212282 19 124 275 TABLE 18Address of Parity Bit Accumulators (Rate
- Coded Block Size 960)424 467 351 278 130 273138 208 267 420 457 470387 230 264 237 68 346450 148 62 67 5 225213 471 123 289159 412 221 434136 479 246 148448 65 213 239 TABLE 19Address of Parity Bit Accumulators (Rate
- Coded Block Size 1440)414 469 23 658 559 44013 322 153 338 220 539567 661 680 386 259 347207 511 215 469 536 42083 295 133 280 363 378713 453 579 307 234 676148 471 150 633509 417 524 696681 360 306 281674 130 544 629252 326 10 46172 122 488 562 TABLE 20Address of Parity Bit Accumulators (Rate
- Coded Block Size 2160)297 811 822 736 708 943786 553 17 33 889 4966 681 597 911911 71 753 446 49 854717
228 1116 572 295 736 517 419164 80 651 937 221 845 537 472 934 172 787 1270 784 605 590766 5 50 426316 146 664 581929 722 251 201324 184 193 60436 81 412 342867 688 819 1141 453 688 63 TABLE 21Address of Parity Bit Accumulators (Rate
- Coded Block Size 2880)101
236 1044486
845 573 140 278 717646 922
231 41 622 392 300 526 196 138748 4 875 552 728 175 826 111708 469 262 501 570 5 7128 836 781 323 1360720 712 36 13885 457689 115 537 995 1 105871 8 83259 785365 819 954 523 781795 401 210 1171 TABLE 22Address of Parity Bit Accumulators (Rate
- Coded Block Size 3600)3 653 1242 3 270
831 5 93667 278 947 473 193 10388 80 78130 323 181 64 8175 133 250 369 6 34 682330 113 4 860897 270
8583 9681 864 0 63889 11108 779 16691 1229434 154 515 1321374 620 321 839 962 1507921 165
30952 8972 929 176 832 7 3666 417 TABLE 23Address of Parity Bit Accumulators (Rate
- Coded Block Size 4320)175 41 262 03 875 522 8969 346 198 451 367 43 601 674 13526 191 383 2007140 562 75 1162879 708 609 37 4 22169 312 386 7 821 569 33 94 915 25 9116 5 745 56 396 64 9 1290 13837 18 13528 588 6 83597 699489 590 980 12 449 0 1316 91002 2053773 728 938 8697 14172 293900 6 TABLE 24Address of Parity Bit Accumulators (Rate
- Coded Block Size 5760)991 3 234 760883
17 477 646 9 273710 14 120 22345 954 44 4 135026 7 177 2031567 48 678
8 696 976 7 2 660 296 980 313956
707 853 295 179 16027 5117 7 198 7
17 17 701 454 7
44 175 838 445126
1463911 45 27614 19461 34761 4506 261818 25920 211247 829 814 28351 510 8 170328 23076 1991 159680 22111 1740 62852 332.
An apparatus comprising: memory configured to store information representing a predetermined structured parity check matrix of a Low Density Parity Check (LDPC) code for encoding information bits, the information representing the structured parity check matrix being organized in tabular form, wherein each row represents occurrences of one values within a respective column of the parity check matrix, wherein the columns of the parity check matrix are derived according to a predetermined operation based on the respective rows of the and an encoder configured to encode the information bits, and to output an LDPC coded signal comprising the encoded information bits, wherein the encoding comprises: initializing parity bit accumulators to zero, accumulating a first information bit in a jth group of M information bits in an ith parity bit accumulator if the ith entry in the (jM)th column of the parity check matrix is 1, where j=0, 1, 2, 3, . . . kldpc/M-1, accumulating the remaining (M-1) information bits m=jM+1, jM+2, jM +3, . . . (j+1)M-1 of the jth group in the parity bit accumulators according to {x+m mod M*q} mod(nldpc-kldpc), wherein x denotes the address of the parity bit accumulator corresponding to the first bit, jM, in the group, and after all of the information bits are exhausted, performing operations, starting with i=1 are performed according to, pM=pM⊕p0 p2M=p2M⊕pM p3M=p3M⊕p2M ??? pnldpc-kldpc-M=pnldpc-kldpc-M⊕pnldpc-kldpc-2M p1=p1⊕pnldpc-kldpc-M pM+1=pM+1⊕p1 p2M+1=p2M+1⊕pM+1 ??? pnldpc-kldpc-M+1=pnldpc-kldpc-M+1⊕pnldpc-kldpc-2M+1 p2=p2⊕pnldpc-kldpc-M+1 pM+2=pM+2⊕p2 p2M+2=p2M+2⊕pM+2 ??? pnldpc-kldpc-M+2=pnldpc-kldpc-M+2⊕pnldpc-kldpc-2M+2 p3=p3⊕pnldpc-kldpc-M+2 pM+3=pM+3⊕p3 p2M+3=p2M+3⊕pM+3 ??? pnldpc-kldpc-M+3=pnldpc-kldpc-M+3⊕pnldpc-kldpc-2M+3 ????? pM-1=pM-1⊕pnldpc-kldpc-2 p2M-1=p2M-1⊕pM-1 P3M-1=p3M-1⊕p2M-1 ??? pnldpc-kldpc-1=pnldpc-kldpc-1⊕pnldpc-kldpc-M-1 wherein final content of pi, i=0, 1, . . . (nlpdc-kldpc-1) is equal to the parity bit pi.
An apparatus according to claim 11, wherein M=360 and coded block size nldpc is 64800 code rates are 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10, respectively.
An apparatus according to claim 11, further comprising: a Bose Chaudhuri Hocquenghem (BCH) transmitter configured to encode an input signal using BCH codes, wherein the output LDPC coded signal corresponding to the input signal represents a code having an outer BCH code and an inner LDPC code.
An apparatus according to claim 11, further comprising: an interleaver configured to interleave the output LDPC and a modulator configured to modulate the interleaved LDPC coded signal based on 8-PSK (Phase Shift Keying) or 16-APSK (Amplitude Phase Shift Keying) modulation scheme, wherein the interleaver is configured to write the LDPC coded signal column-wise and to read an interleaved output LDPC coded signal row-wise, from left to right, and wherein if an 8-PSK modulation scheme is used for a code rate 3/5, the interleaved output LDPC coded signal is read from right to left.
An apparatus according to claim 11, wherein the tabular information representing the structured parity check matrix comprises a one of Tables 25 through 35 (below), wherein the row indices of 1's in the column index j*M, (j=0, 1, 2, 3, . . . kldpc/360-1) of the parity check matrix are given at the jth row according to the one Table, and wherein kldpc is associated with a lengt TABLE 25Address of Parity Bit Accumulators (Rate 9/10 - Coded Block Size 64800)853 1589 5634956 2662 6167739 4765 627045 5151860 11369 46122 16262 9333 3244540 5363 5842126 535 450 1049 5772234 321803233 447 2661407 915364753 882 476 145884 94160 26219682340 278 154 585206765 23176329429 741 2271419 595 855 7946875 305 22473 86 433 6038771 60151 584 361071558330239550269 604 191871247 788 180926796 406 812 3768259699271 360 4695216651601319550 415 8270192727010648813 39517 0 23274 745 4778319 807 462521296 607 66331896586073162 871 213571 32367 104603459 229 197 671 2247427037382 815 84122047362 5525305 96796 958 021645 12501990129 6442457 81160 659 2182641 4507853 966
TABLE 26Address of Parity Bit Accumulators (Rate 8/9 - Coded Block Size 64800)71 539561 651909 602483 708887 701017 527462 396101 6537309 60126 09300 558 18 641923 66350 24582 11957 1455 4994998 66519 24534 873 578 945 21 670368 62354 67350 96396 3418 695368 464562 3781840 3563 695930 6336180 1195 5046371 949 712 6339 617429 618046 552442 7165523 7499 5006450 754 61 7120 7067872 6059 628473 598193 447659 408168 559562 19248 650 04 56426 3732 699580 681599 635132 6942562 65311 112 530 756076975 9191717 02852 081374212 923 6113370 942579 550 15829995827 325 61990241202 719 544984459 742 976 594880358859340 488 17023430 579 785 386928785 971 597 299 751259625006782010352 655 950 98367 229620317 2295351328961 62233 800 88585 58112 110 3611210 459 15630866586 18289655557172620 768 60581532876
TABLE 27Address of Parity Bit Accumulators (Rate
- Coded Block Size 64800)214 03 94 96 67 6944 89 5061 27 65992 53 83 53 82 61 549 60 34 435 93 84 24 90 1132 52 00 501 82 19 556 00 89 30 98
10643188 65 15 265 57 98 236 96 34 529 16 97 43 922 36 196 10528692 46 62 632 50 88 4 936 54 86 814118 424 17 68 943608 67 00848 68 40899 23
10647741 93 56 54 57 10376 908 31 83 8778987 43 57 966 73 74 47908316386342 786230 46699 627 747 4057360 428 101192027167745 83880 502099846622766214 24875314857575278 277 2984571732243823 783 32792509810 637 5827184702 692 14958 2815875110992 1450676832656 3005611901968 0828323 607 1070183 352 408655 13307788739 58211 788 106940645538619 577 5095471029248 768 017618890 77605558271530428 324094418 TABLE 28Address of Parity Bit Accumulators (Rate
- Coded Block Size 64800)88 40
1293689 71 12
37 58 850 95 91 93 706 11883476 913 79 67
12888468 74 29 577 1272863 955 13 88
1239819 11
1265380 41 86
437 982 71 377
1226002 28 533 46 81 79 96 11775188 24 01
346 668 925 20 570 13 97 52 72 74
11823980 15 58
58 80 12 69640 42259375 998 807 3000558022195570698 44150524081699123 1194816253704451939331 623 50474 871009 10869856 05775796830 855747 7093124401602153 663669771329 409 976 57876 311964975813435769756132 1178785399 928981333 55929708771 129062916552594028143 136 715 477925900611 51862 11971 11718 12924543368238834242 75 12906412 12664497523 01498 19871 642684095530335437640 306527091 595292 70 TABLE 29Address of Parity Bit Accumulators (Rate 3/4 - Coded Block Size 64800)89
15673164 17 67
1605049 967
257 55 43 50 70 65 02
1476892 93
1585653 07
13859891 09 97 12 625 83 26
1512491 58 463
14267358 594 55 328
860 68 22 52 498
12022546 15688 12643284468413661 811 159 14909 1343416089 14377153 687 859701 1480196702 30 1585803186243323 12635 1497128659622 1589255368842835878623 13847244 12890 1313241
13846 16119 15794461426050 15695791655 660810 13767725 14604878993303 20309984935115 188648 602 988 44972 807 931 15238 15553 15637 130407 767054541 231557096663 417 16104939279717 734 91 15553 1190032699
13789366054 1343679875380306 956929856599247671942949
1101568 TABLE 30Address of Parity Bit Accumulators(Rate 2/3 - Coded Block Size 64800)186
29 496 2093245
54 788 19387257
30 108 1651755
603 53 80022
20934200 68
40345937083 20123404823
18118 19524 11405493
16865344 17544 18443 20689 14306 15930 14361 19136672 20412 20284314 718870180 334186
21593116 17920226 18444 21397 14678118 735584 20027 21258 2121964 11712 16156 16655 177063251856 18850874876 14312 19036 20068938
15341 18913 17541 12365396 070 15008 19548 20525697 20406 20942 13410152
17236216 54085 21560 2104710365709 177961900
19778 12317 20332 18027644 595005 TABLE 31Address of Parity Bit Accumulators(Rate 3/5 - Coded Block Size 64800)
1995775 53
57 646 467
24267902 30
22010939 512
2255027 970 541 924 37
21840378 80
588 857 13 54 12848 24447 22074082564 24211341 323
22658 13320289 533
2002875 21282 24968665602 20657 24693 23813 21530 23406 25283 12236 21017 25712353 15312495 15270 25869 2206992553 25599591673386 20518644 20440 18267 19917 24520 15040144 13867 22746628
18998719729 20091849 21754 22399893
17456 24063488 757 16932 23973 24978782
23080 15669 17284 23285 TABLE 32Address of Parity Bit Accumulators(Rate 1/2 - Coded Block Size 64800)
30963347 71
31413876 22
2357490 792
15275303 27550 20167329
30914 26143 29562423 31855250 21323 29095 32396 30015 25755 30378259 24705854078 25612 29625 20819541 27847249 30933 29543 30687 2086357 25761 19685 20662 19410 32037793
2320134987 24186 28552 25266 23870754 21285221 28651619
30849 32018271612
25651 23874 26533454
31936 20152 TABLE 33Address of Parity Bit Accumulators(Rate 2/5 - Coded Block Size 64800) 62
3291033 81 348
3472109 790
35802672 040
15412 30469494 37078 29341 21979026 37489253 38608 25368466 35696 19353442 838 26339 38759 14717 38419 38114 21066731 632 17631 34050747 36329 22488 36004 32363 14033 31025 38569 21031 34436 28666 30092837399
36108 27403 23361 33457 20421 32359 30059 31348 32657 TABLE 34Address of Parity Bit Accumulators(Rate 1/3 - Coded Block Size 64800)37
3688364 58
3831476 932
42874296 82 414
42681976 64
42109 35811 34952411 41783 35897 36715 41196 34976 32912 29630 32046 32622 37743 18132 29644 36470 20405 23944 32227 32862 34431 37568 21514 28406 38951 41428 33758 39284 41788 41111 33923 36184 40480 27939 41661 24200 42660331 31360 19794 TABLE 35Address of Parity Bit Accumulators(Rate 1/4 - Coded Block Size 64800) 407 004
46447122 53
47137572 90
4338867 19 009
42413 27784 48159 38594 34900 24603 27441 43211210
31602 29610 37802606 47221 44496 42727 47800 43721686 47500 44968 43948429 45622 47703 44970 45392 44279 45118 45091.
An apparatus according to claim 15, wherein M=360 and coded block size nldpc is 64800 code rates are 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10, respectively.
An apparatus according to claim 15, further comprising: a Bose Chaudhuri Hocquenghem (BCH) transmitter configured to encode an input signal using BCH codes, wherein the output LDPC coded signal corresponding to the input signal represents a code having an outer BCH code and an inner LDPC code.
An apparatus according to claim 15, further comprising: an interleaver configured to interleave the output LDPC and a modulator configured to modulate the interleaved LDPC coded signal based on 8-PSK (Phase Shift Keying) or 16-APSK (Amplitude Phase Shift Keying) modulation scheme, wherein the interleaver is configured to write the LDPC coded signal column-wise and to read an interleaved output LDPC coded signal row-wise, from left to right, and wherein if an 8-PSK modulation scheme is used for a code rate 3/5, the interleaved output LDPC coded signal is read from right to left.
A method according to claim 6, further comprising: encoding an input signal according to Bose Chaudhuri Hocquenghem (BCH) codes, wherein the output LDPC coded signal corresponding to the input signal represents a code having an outer BCH code and an inner LDPC code.
A method according to claim 19, wherein the number of redundant BCH bits is nBCH-kBCH=192 and error correction capability of the BCH code is 12 bits.
A method according to claim 6, further comprising: interleaving the output LDPC coded signal
and modulating the interleaved LDPC coded signal based on 8-PSK (Phase Shift Keying) or 16-APSK (Amplitude Phase Shift Keying) modulation scheme, wherein the interleaving comprises writing the LDPC coded signal into the interleaver column-wise and reading an interleaved output LDPC coded signal row-wise, from left to right, and wherein if an 8-PSK modulation scheme is used for a code rate 3/5, the interleaved output LDPC coded signal is read from right to left.
Description:
BACKGROUND OF THE INVENTIONCommunication systems employ coding to ensure reliable communication across noisy communication channels. These communication channels exhibit a fixed capacity that can be expressed in terms of bits per symbol at certain signal to noise ratio (SNR), defining a theoretical upper limit (known as the Shannon limit). As a result, coding design has aimed to achieve rates approaching this Shannon limit. One such class of codes that approach the Shannon limit is Low Density Parity Check (LDPC) codes.Traditionally, LDPC codes have not been widely deployed because of a number of drawbacks. One drawback is that the LDPC encoding technique is highly complex. Encoding an LDPC code using its generator matrix would require storing a very large, non-sparse matrix. Additionally, LDPC codes require large bl consequently, even though parity check matrices of LDPC codes are sparse, storing these matrices is problematic.From an implementation perspective, a number of challenges are confronted. For example, storage is an important reason why LDPC codes have not become widespread in practice. Also, a key challenge in LDPC code implementation has been how to achieve the connection network between several processing engines (nodes) in the decoder. Further, the computational load in the decoding process, specifically the check node operations, poses a problem.Therefore, there is a need for an LDPC communication system that employs simple encoding and decoding processes. There is also a need for using LDPC codes efficiently to support high data rates, without introducing greater complexity. There is also a need to improve performance of LDPC encoders and decoders. There is also a need to minimize storage requirements for implementing LDPC coding. There is a further need for a scheme that simplifies the communication between processing nodes in the LDPC decoder.SOME EXEMPLARY EMBODIMENTSThese and other needs are addressed by the present invention, wherein various approaches for encoding and decoding structured Low Density Parity Check (LDPC) codes is provided.According to one aspect of an exemplary embodiment, a method comprises accessing memory storing information representing a structured parity check matrix of Low Density Parity Check (LDPC) codes. The information is organized in tabular form, such each row represents occurrences of one value within a first column of a group of columns of the parity check matrix, the rows correspond to groups of columns of the parity check matrix. Also, subsequent columns within each of the groups are derived according to a predetermined operation. Further, an LDPC coded signal is outputted based on the stored information representing the parity check matrix. Parity bit accumulators are to initialized to zero, and first information bit in the jth group of M information bits is accumulated in the ith parity bit accumulator if the ith entry in (jM)th column of the parity check matrix is 1, where j=0, 1, 2, 3, . . . kldpc/M-1, the remaining (M-1) information bits m=jM+1, jM+2, jM+3, . . . , (j+1)M-1 of the jth group being accumulated in the parity bit accumulators according to {x+m mod M×q} mod(nldpc-kldpc), wherein x denotes the address of the parity bit accumulator corresponding to the first bit, jM, in the group, andq=nldpc-kldpcM
is a code rate dependent constant, and after all of the information bits are exhausted, operations, starting with i=1 are performed according to p1=p1⊕p1-1, 2, . . . , nldpc-kldpc-1, wherein final content of p1=0, 1, . . . , nldpc-kldpc-1 is equal to the parity bit p1. According to another aspect of an exemplary embodiment, an apparatus comprises a memory which is configured to store information representing a structured parity check matrix of Low Density Parity Check (LDPC) codes. The information is organized in tabular form, wherein each row represents occurrences of one values within a first column of a group of columns of the parity check matrix. Also, the rows correspond to groups of columns of the parity check matrix, where subsequent columns within each of the groups are derived according to a predetermined operation. The apparatus also comprises circuitry coupled to the memory and configured to output an LDPC coded signal using the stored information representing the parity check matrix. Parity bit accumulators are to initialized to zero, and first information bit in the jth group of M information bits is accumulated in the ith parity bit accumulator if the ith entry in (jM)th column of the parity check matrix is 1, where j=0, 1, 2, 3, . . . kldpc/M-1, the remaining (M-1) information bits m=jM+1, jM+2, jM+3, . . . , (j+1)M-1 of the jth group being accumulated in the parity bit accumulators according to {x+m mod M×q} mod(nldpc-kldpc), wherein x denotes the address of the parity bit accumulator corresponding to the first bit, jM, in the group, andq=nldpc-kldpcM
is a code rate dependent constant, and after all of the information bits are exhausted, operations, starting with i=1 are performed according to p1=p1⊕i=1, 2, . . . , nldpc-kldpc-1, wherein final content of p1, i=0, 1, . . . , nldpc-kldpc-1 is equal to the parity bit pi. According to another aspect of an exemplary embodiment, a method comprises accessing memory storing edge information associated with a structured parity check matrix used to generate Low Density Parity Check (LDPC) coded signal. The edge information represent relationship between bit nodes and check nodes, and are stored according to a predetermined scheme that permits concurrent retrieval of a set of the edge information. Further, a decoded signal is outputted corresponding to the LDPC coded signal based on the stored edge information.According to another aspect of an exemplary embodiment, a method comprises accessing memory storing edge information and a posteriori probability information associated with a structured parity check matrix used to generate Low Density Parity Check (LDPC) coded signal. The edge information represents relationship between bit nodes and check nodes, and are stored according to a predetermined scheme that permits concurrent retrieval of a set of the edge information. Further, a decoded signal is outputted corresponding to the LDPC coded signal based on the stored edge and a posteriori probability information.Still other aspects, features, and advantages of the present invention are readily apparent from the following detailed description, simply by illustrating a number of particular embodiments and implementations, including the best mode contemplated for carrying out the present invention. The present invention is also capable of other and different embodiments, and its several details can be modified in various obvious respects, all without departing from the spirit and scope of the present invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as restrictive.BRIEF DESCRIPTION OF THE DRAWINGSThe present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:FIG. 1 is a diagram of a communications system configured to utilize Low Density Parity Check (LDPC) codes, according to an FIGS. 2A-2D are diagrams of exemplary LDPC encoders deployed in the transmitter of FIG. 1 and exemplary encoding processes, according to various eFIG. 3 is a diagram of an exemplary receiver in the system of FIG. 1, according to an FIG. 4 is a diagram of a sparse parity check matrix, according to an FIG. 5 is a diagram of a bipartite graph of an LDPC code of the matrix of FIG. 4, according to an FIG. 6 is a diagram of a sub-matrix of a sparse parity check matrix, wherein the sub-matrix contains parity check values restricted to the lower triangular region, according to an FIGS. 7A-7C are, respectively, a diagram of a quadrature phase-shift keying (QPSK), an 8-PSK, and a 16 amplitude and phase-shift keying (16-APSK) modulation scheme, respectively, each of which can be used in the system of FIG. 1, according to an FIGS. 8A and 8B are flowcharts of processes for computing outgoing messages between the check nodes and the bit nodes using, respectively, a forward-backward approach and an enhanced layered belief decoding (LBD) scheme, according to various eFIGS. 9A-9C are diagrams of the interactions between the check nodes and the bit nodes in a decoding process, according to an FIG. 10 is a graph illustrating simulation results for the enhanced LBD scheme, according to an FIG. 11 is a graph showing simulation results of LDPC codes generated in accordance with various eFIGS. 12A and 12B are diagrams of the top edge and bottom edge, respectively, of memory organized to support structured access as to realize randomness in LDPC coding, according to an FIGS. 13A-13D are diagrams of parity check matrix, bipartite graph, top edge RAM, and bottom edge RAM, respectively, to support structured access as to realize randomness in LDPC coding/decoding, according to an FIGS. 14A-14C are diagrams of the edge, a posteriori, and shifted a posteriori, respectively, of memory organized to support LDPC decoding, according to an exemplary embodiment.FIGS. 15A-15C are graphs showing simulation results of LDPC codes generated in accordance with various e andFIG. 16 is a diagram of a computer system that can perform the processes of encoding and decoding of LDPC codes, in